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US 2014/0177371 A1Published application
Suspend sdram refresh cycles during normal ddr operation
AssigneeLSI Corporation
InventorsJackson L. Ellis, Shruti Sinha
Life of this patent
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Abstract
An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.
Claims9
An apparatus comprising:
- a built in self test (GIST) engine configured to generate a plurality of control signals in response to one or more read data signals;
- and
- a protocol engine configured to generate a plurality of interface signals in response to said plurality of control signals, wherein said protocol engine suspends a refresh operation during a normal operation of said apparatus.
An apparatus for implementing a controller in an SDRAM, comprising the steps of:
- means for generating a plurality of control signals in response to one or more read data signals;
- and
- means for generating a plurality of interface signals in response to said plurality of control signals, wherein said apparatus suspends a refresh operation during a normal operation of said apparatus.
A method for implementing a controller in an SDRAM, comprising the steps of:
- (A) generating a plurality of control signals in response to one or more read data signals;
- and
- (B) generating a plurality of interface signals in response to said plurality of control signals, wherein said method suspends a refresh operation during a normal operation of said apparatus.
Dependencies are inferred from the claim text.