Data input/output circuit and semiconductor memory device including the same
AssigneeSK hynix Inc.
InventorSung Soo CHI
Life of this patent
Estimating the term…
Abstract
A data input/output circuit includes a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in a standby state, and supply the precharge voltage driven by a second internal voltage when an active operation is performed; and a precharge unit configured to receive the precharge voltage, precharge a first input/output line and a first inverted input/output line to a level of the first internal voltage in the standby state, and precharge the first input/output line and the first inverted input/output line by the second internal voltage when the active operation is performed.
Claims32
A data input/output circuit comprising:
- a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in a standby state, and supply the precharge voltage driven by a second internal voltage when an active operation is performed;
- and
- a precharge unit configured to receive the precharge voltage, precharge a first input/output line and a first inverted input/output line to a level of the first internal voltage in the standby state, and precharge the first input/output line and the first inverted input/output line by the second internal voltage when the active operation is performed.
A data input/output circuit comprising:
- a control signal generation unit configured to generate a first control signal enabled in a standby state, a second control signal enabled when a read operation is performed, a third control signal enabled when data is outputted in the read operation, and a third inverted control signal, in response to an active command, a read command and a precharge command;
- and
- a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in the standby state, and supply the precharge voltage driven by a second internal voltage when an active operation is performed, in response to the first and second control signals.
A semiconductor memory device comprising:
- a cell block including a plurality of memory cells;
- a word line driver positioned adjacent to the cell block in a first direction, and configured to drive a word line for accessing a memory cell included in the cell block;
- a sense amplifier positioned adjacent to the cell block in a second direction, and configured to sense and amplify a first input/output line and a first inverted input/output line on which data outputted from the accessed memory cell is loaded, in response to an output select signal in a read operation;
- and
- a data input/output circuit positioned adjacent to the word line driver in the second direction and adjacent to the sense amplifier in the first direction, and configured to transfer the data loaded on the first input/output line and the first inverted input/output line to a second input/output line and a second inverted input/output line,
- wherein the data input/output circuit precharges the first input/output line and the first inverted input/output line by a level of a first internal voltage in a standby state, and precharges the first input/output line and the first inverted input/output line by a second internal voltage when an active operation is performed.
Dependencies are inferred from the claim text.