Semiconductor apparatus, test method using the same and muti chips system

A semiconductor apparatus comprising:

• a first memory die configured to be enabled in response to a first memory die activation code;
• a second memory die configured to be enabled in response to a second memory die activation code, and disposed on the first memory die;
• a first TSV configured to couple the first and second memory dies;
• and
• a second TSV configured to couple the first and second memory dies,
• wherein the first memory die comprises first and second test units, activates one of the first and second test units in response to the first memory die activation code, and outputs a test result of the first memory die through the first TSV, and
• the second memory die comprises third and fourth test units, activates one of the third and fourth test units in response to the second memory die activation code, and outputs a test result of the second memory die through the second TSV.

A test method of a semiconductor apparatus, comprising the steps of:

• storing the same data in first and second memory dies during a test;
• providing a first memory die activation code to the first memory die and providing a second memory die activation code to the second memory die so as to activate both of the first and second memory dies;
• activating one of a plurality of test units included in the first memory die in response to the first memory die activation code;
• activating one of a plurality of test units included in the second memory die in response to the second memory die activation code;
• determining whether all of data outputted from the first memory die are identical or not, through an activated test unit included in the first memory die, and outputting the determination result through a first data input/output TSV;
• and
• determining whether all of data outputted from the second memory die are identical or not, through an activated test unit included in the second memory die, and outputting the determination result through a second data input/output TSV.

A multi chips system, comprising:

• a plurality of chips configured to be stacked;
• a plurality of TSV configured to form to penetrate the plurality of chips;
• and
• a plurality of test units configured to form in every chip, and couple the plurality of TSV, respectively,
• wherein one of the plurality of test units which is formed in the same chip is configured to select in every chip, to generate a test result, and the test result is outputted through a selected TSV coupled to the selected test unit.