Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit

A method for controlling a delay locked loop in a synchronous memory device, the delay locked loop having a delay line, and the method comprising:

• receiving an external clock signal;
• applying the external clock signal to the input of the delay line;
• in response to a read command:
• configuring the delay locked loop in a first mode of operation to provide an internal clock, from an output of the delay line to an output circuit, locked to the external clock;
• and
• configuring the output circuit to output read data to an output terminal in synchronization with the internal clock;
• and
• in response to an on-die-termination command:
• configuring the delay locked loop in a second mode of operation to provide the internal clock locked to the external clock to the output circuit;
• and
• configuring the output circuit to terminate the output terminal in synchronization with the internal clock;
• and
• the delay locked loop controls the phase of the internal clock in a more precise manner in the first mode of operation compared to the second mode of operation, and
• the delay locked loop consumes less power in the second mode of operation as compared to the first mode of operation.