Method and apparatus for aligning a clock signal and a data strobe signal in a memory system

Apparatus comprising a memory controller and a memory, the apparatus comprising:

• a control unit configured to put said memory into a write levelling mode;
• an alignment delay determination unit configured to increment an alignment delay applied to said data strobe signal until a transition point occurs at which a response of said memory to issuance of said data strobe signal transitions to an inverse state;
• an oversampling unit configured to perform an oversampling of said response of said memory over a selected interval following said transition point,
• said alignment delay determination unit and said oversampling unit configured to repeat said incrementing and performing an oversampling until, for a selected alignment delay, a majority of results of said oversampling is in said inverse state;
• and
• a cycle alignment detection unit configured to perform a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of said clock signal which is responsible for said transition point,
• wherein said control unit is configured to apply said selected alignment delay to said data strobe signal and to apply a clock cycle selection to a data path to match said identified clock cycle.

Apparatus comprising a memory controller and a memory, the apparatus comprising:

• control means for putting said memory into a write levelling mode;
• alignment delay determination means for incrementing an alignment delay applied to said data strobe signal until a transition point occurs at which a response of said memory to issuance of said data strobe signal transitions to an inverse state;
• oversampling means for performing an oversampling of said response of said memory over a selected interval following said transition point means configured to repeat said incrementing and performing an oversampling until, for a selected alignment delay, a majority of results of said oversampling is in said inverse state;
• and
• cycle alignment detection means for performing a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of said clock signal which is responsible for said transition point,
• wherein said control means is configured to apply said selected alignment delay to said data strobe signal and to apply a clock cycle selection to a data path to match said identified clock cycle.