Zero keeper circuit with full design-for-test coverage

A method of controlling an output of a zero keeper circuit, the zero keeper circuit comprising a dynamic input PFET connected to a power source and a zero keeper output, wherein the dynamic input PFET is configured to couple the power source to the zero keeper output based on a dynamic input;

• a clock input NFET connected to the zero keeper output and a pull-down node, wherein the clock input NFET is configured to couple the zero keeper output to the pull-down node based on a clock input;
• a dynamic input NFET connected to the pull-down node and a reference voltage, wherein the dynamic input NFET is configured to couple the pull-down node to the reference voltage based on the dynamic input;
• a feedback PFET and a clock input PFET connected in series between the power source and the zero keeper output, wherein the feedback PFET is selectively enabled based on a feedback signal and the clock input PFET is selectively enabled based on the clock input;
• a feedback NFET connected to the zero keeper output and the pull-down node, wherein the feedback NFET is configured to couple the zero keeper output to the pull-down node based on the feedback signal;
• and a NOR gate configured to output the feedback signal based on the zero keeper output and a bypass input, the method comprising forcing the zero keeper output to a logic high, including:
• setting the bypass input to a logic high;
• and
• holding the clock input to a logic low.

A device comprising:

• a memory array;
• and
• a zero keeper circuit coupled to a read output of the memory array, wherein the zero keeper circuit comprises:
• a dynamic input PFET connected to a power source and a zero keeper output, wherein the dynamic input PFET is configured to couple the power source to the zero keeper output based on a dynamic input;
• a clock input NFET connected to the zero keeper output and a pull-down node, wherein the clock input NFET is configured to couple the zero keeper output to the pull-down node based on a clock input;
• a dynamic input NFET connected to the pull-down node and a reference voltage, wherein the dynamic input NFET is configured to couple the pull-down node to the reference voltage based on the dynamic input;
• a feedback PFET and a clock input PFET connected in series between the power source and the zero keeper output, wherein the feedback PFET is selectively enabled based on a feedback signal and the clock input PFET is selectively enabled based on the clock input;
• and
• a feedback NFET connected to the zero keeper output and the pull-down node, wherein the feedback NFET is configured to couple the zero keeper output to the pull-down node based on the feedback signal;
• and a NOR gate configured to output the feedback signal based on the zero keeper output and a bypass input.

A memory apparatus comprising:

• an array of memory cells;
• a read output;
• and
• a zero keeper circuit coupled to the read output, wherein the zero keeper circuit comprises:
• a dynamic input PFET connected to a power source and a zero keeper output, wherein the dynamic input PFET is configured to couple the power source to the zero keeper output based on a dynamic input;
• a clock input NFET connected to the zero keeper output and a pull-down node, wherein the clock input NFET is configured to couple the zero keeper output to the pull-down node based on a clock input;
• a dynamic input NFET connected to the pull-down node and a reference voltage, wherein the dynamic input NFET is configured to couple the pull-down node to the reference voltage based on the dynamic input;
• a feedback PFET and a clock input PFET connected in series between the power source and the zero keeper output, wherein the feedback PFET is selectively enabled based on a feedback signal and the clock input PFET is selectively enabled based on the clock input;
• and
• a feedback NFET connected to the zero keeper output and the pull-down node, wherein the feedback NFET is configured to couple the zero keeper output to the pull-down node based on the feedback signal;
• and a NOR gate configured to output the feedback signal based on the zero keeper output and a bypass input.