US 2014/0177350 A1 · SINGLE-ENDED SENSE AMPLIFIER CIRCUIT

Abstract

A single-ended sense amplifier and a method for reading a memory cell are disclosed. The method includes the following steps. A bit line is charged according to a control signal. Thereafter, whether the dropoff time of the bit line voltage is greater or less than a predetermined time is deteremined. When the dropoff time of the voltage of the bit line is less than the predetermined time period, a first operation is sensed. On the other hand, when the dropoff time of the voltage of the bit line is greater than the predetermined time period, a second operation is sensed. The dropoff time of the voltage of the bit line is determined according to a parasitic capacitance on the bit line. A logic level of a sensing transistor circuit is retained and an output data signal according to the operation sensed is generated.

Claims14

Dependent claims

A single-ended sense amplifier circuit, comprising:

a pre-charge circuit coupled to a bit line to charge the bit line according to a control signal;
a sensing transistor circuit coupled to the bit line to read a memory cell;
and
a latch circuit coupled to the sensing transistor circuit to retain a logic level of the sensing transistor circuit and to generate an output data signal acccording to an operation sensed,
wherein when a dropoff time of a voltage of the bit line is less than a predetermined time period, a first operation is sensed by the sensing transistor circuit, and when the dropoff time of the voltage of the bit line is greater than the predetermined time period, a second operation is sensed by the sensing transistor circuit, and the dropoff time of the voltage of the bit line is determined according to a parasitic capacitance on the bit line.

2 more elements

Dependencies are inferred from the claim text.

Single-ended sense amplifier circuit

Life of this patent

Single-ended sense amplifier circuit

Life of this patent

Abstract

Claims14