Method and apparatus for clock power saving in multiport latch arrays

An apparatus comprising:

• an integrated circuit (IC) element comprising:
• means for storing data;
• a P-type semiconductor region comprising a first semiconductor means from a first memory port circuit coupled to the means for storing data, the first semiconductor means configured to enable the first memory port circuit to provide access to the means for storing data when the first semiconductor means is activated;
• an N-type semiconductor region comprising a second semiconductor means from a second memory port circuit coupled to the means for storing data, the second semiconductor means configured to enable the second memory port circuit to provide access to the means for storing data when the second semiconductor means is activated;
• and
• means for distributing signals over the P-type and N-type semiconductor regions of the IC element comprising:
• a first memory port selection means for activating the first semiconductor means;
• a second memory port selection means for activating the second semiconductor means;
• and
• a clock signal distribution means for providing timing information to the IC element, the clock signal distribution means being placed between the first memory port selection means and the second memory port selection means.

A method for forming a memory apparatus comprising:

• arranging a set of integrated circuit (IC) elements, each IC element comprising a memory device comprising:
• a first memory port circuit comprising a first memory port enable node coupled to a first semiconductor device configured to enable access to the memory device, wherein the first memory port enable node is located in a P-type semiconductor region;
• and,
• a second memory port circuit comprising a second memory port enable node coupled to a second semiconductor device configured to enable access to the memory device, wherein the second memory port enable node is located in an N-type semiconductor region;
• routing a first memory port selection signal line in the P-type semiconductor region to connect to the first memory port enable node of at least two first memory port circuits;
• routing a second memory port selection signal line in the N-type semiconductor region to connect to the second memory port enable node of at least two second memory port circuits;
• and,
• routing a clock signal line between the first memory port selection signal line and the second memory port selection signal line to connect to the set of IC elements.