Memory device with high-speed reading function and method thereof

A memory device, comprising:

• a first memory cell array, comprising a plurality of first word lines and a plurality of first bit lines, wherein a plurality of first data are stored in the first memory cell array;
• a second memory cell array, separated from the first memory cell array, and comprising a plurality of second word lines and a plurality of second bit lines, wherein a plurality of second data are stored in the second memory cell array;
• a control logic circuit, allowed to select one of the first word lines and one of the second word lines at a same time or an overlapping time, and alternately selecting a first address of the first memory cell array and a second address of the second memory cell array such that a first corresponding portion of the first data and a second corresponding portion of the second data are alternately read from the first memory cell array and the second memory cell array;
• a first sense amplifier, coupled via the first bit lines to the first memory cell array, and amplifying the first corresponding portion of the first data;
• and
• a second sense amplifier, coupled via the second bit lines to the second memory cell array, and amplifying the second corresponding portion of the second data.