Nonvolatile semiconductor memory device and memory system having the same

A memory system comprising:

• a nonvolatile semiconductor memory unit;
• and
• a controller,
• wherein the nonvolatile semiconductor memory unit includes:
• a first memory cell array including at least one first string group constituted of a plurality of first strings, each of the first strings including a first number of first memory cells each storing therein information in a nonvolatile manner, each of the first memory cells being connected to an associated one of a plurality of first word lines;
• a second memory cell array including at least one second string group constituted of a plurality of second strings, each of the second strings including a second number of second memory cell or cells each storing therein information in a nonvolatile manner, the second number being smaller than the first number, each of the second memory cell or cells being connected to a second word line or an associated one of a plurality of second word lines;
• a first bit line connected to one of the first strings;
• a second bit line connected to one of the second strings;
• and
• a page buffer that stores therein data read from the first and second memory cell arrays via the first and second bit lines, respectively,
• wherein the controller controls access to the first and/or second memory cell arrays,
• the nonvolatile semiconductor memory unit further includes an external terminal connected to the controller, and
• the controller controls a level of a signal supplied to the external terminal in response to selection of an access target between the first and second memory cell arrays.

A system comprising:

• a nonvolatile memory device comprising
• a first memory array including a first memory string including a first number of first memory cells,
• a second memory array including a second memory string including a second number of second memory cells, the second number being smaller than the first number, and
• a memory terminal;
• and
• a controller device comprising a controller terminal coupled to the memory terminal, and the controller terminal configured to provide a selected one of the first and second memory arrays so that the controller device accesses the selected one of the first and second memory arrays.