Row decoding circuit and memory

A memory comprising a dual-bit split gate flash memory array and a row decoding circuit adapted for providing a word line operation voltage and a control-gate line operation voltage to the dual-bit split gate flash memory array, wherein the row decoding circuit comprises a dummy row decoding unit, at least one row decoding unit and a driving voltage generating circuit,

• wherein the dummy row decoding unit comprises a first dummy control-gate line voltage output, a second dummy control-gate line voltage output and at least one dummy word line voltage output, the first dummy control-gate line voltage output is connected to a control gate line which is connected to a first memory bit of each memory unit of a dummy memory array, the second dummy control-gate line voltage output is connected to a control gate line which is connected to a second memory bit of each memory unit of the dummy memory array, the at least one dummy word line voltage output is connected to a word line which is connected to each row of memory units of the dummy memory array, wherein the dummy memory array comprises at least one row of memory units of the dual-bit split gate flash memory array;
• wherein the row decoding unit comprises a first control-gate line voltage output, a second control-gate line voltage output and at least one word line voltage output, the first control-gate line voltage output is connect to a control-gate line which is connected to a first memory bit of each memory unit of a corresponding memory block, the second control-gate line voltage output is connected to a control-gate line which is connected to a second memory bit of each memory unit of the corresponding memory block, the at least one word line voltage output is connected to each row of memory units of the corresponding memory block, wherein the memory block comprises at least one row of memory units of the dual-bit split gate flash memory array;
• wherein the driving voltage generating circuit is adapted for providing a third driving voltage to the first control-gate line voltage output and the second control-gate line voltage output, the driving voltage generating circuit comprises a first voltage division unit, a second voltage division unit, a first comparison unit, and a second comparison unit, a control unit and a selection unit;
• wherein the first voltage division unit is adapted for dividing a voltage of the first dummy control-gate line voltage output to obtain a first divided voltage, the second voltage division unit is adapted for dividing a voltage of the second dummy control-gate line voltage output to obtain a second divided voltage;
• wherein the first comparison unit is adapted for comparing the first divided voltage and a reference voltage, and outputting a first comparison result, the second comparison unit is adapted for comparing the second divided voltage and the reference voltage, and outputting a second comparison result;
• wherein the control unit is adapted for outputting a control signal based on the first comparison result and the second comparison result which are input to the control unit, and the selection unit is adapted for selecting a first voltage or a second voltage as the third driving voltage under control of the control signal, wherein the first voltage is higher than the second voltage and the second voltage is higher than the reference voltage.