Single-Port Read Multiple-Port Write Storage Device Using Single-Port Memory Cells

A memory operative to provide single-port read multiple-port write functionality, the memory comprising:

• a first memory array, the first memory array comprising at least a first single-port memory cell and a second single-port memory cell, the second single-port memory cell storing data in response to a memory access conflict associated with the first single-port memory cell during a memory cycle;
• a second memory array, the second memory array storing location information associated with data stored in the first and second single-port memory cells;
• and
• a controller operatively coupled to the first and second memory arrays, the controller resolving the memory access conflict by determining locations to store data in the first single-port memory cell and the second single-port memory cell to avoid a collision between concurrent memory accesses to the first single-port memory cell in response to the memory access conflict, the controller determining locations to store data in the first single-port memory cell and the second single-port memory cell based on the location information, the controller determining locations to access data stored in the first single-port memory cell and the second single-port memory cell as a function of the location information.

An electronic system, comprising:

• an integrated circuit, the integrated circuit comprising at least one memory operative to provide single-port read multiple-port write functionality, the at least one memory comprising:
• a first memory array, the first memory array comprising at least a first single-port memory cell and a second single-port memory cell, the second single-port memory cell storing data in response to a memory access conflict associated with the first single-port memory cell during a memory cycle;
• a second memory array, the second memory array storing location information associated with data stored in the first and second single-port memory cells;
• and
• a controller operatively coupled to the first and second memory arrays, the controller resolving the memory access conflict by determining locations to store data in the first single-port memory cell and the second single-port memory cell to avoid a collision between concurrent memory accesses to the first single-port memory cell in response to the memory access conflict, the controller determining locations to store data in the first single-port memory cell and the second single-port memory cell based on the location information, the controller determining locations to access data stored in the first single-port memory cell and the second single-port memory cell as s function of the location information.