Semiconductor memory apparatus, verify read method and system
AssigneeResearch & Business Foundation Sungkyunkwan University
InventorsKeewon KWON, Jongmin BAEK, Dongjin SEO
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Abstract
Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells. Therefore, data of the memory is discriminated by analyzing distribution of the digital code values to monitor a characteristic of a current memory cell array and read the data having reliability.
Claims20
A semiconductor memory apparatus, comprising:
- a memory cell array including a plurality of resistive memory cells;
- and
- a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells.
A verify read method of a semiconductor memory apparatus, comprising:
- generating digital code values reflecting resistance states of a plurality of resistive memory cells;
- and
- controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells.
A semiconductor memory system, comprising:
- a semiconductor memory apparatus;
- and
- a processor for controlling a write operation and a verify read operation of the semiconductor memory apparatus,
- wherein the semiconductor memory apparatus includes
- a memory cell array including a plurality of resistive memory cells;
- and
- a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells.
Dependencies are inferred from the claim text.