Semiconductor memory devices and semiconductor system having parameters, and methods of testing the same
AssigneeSK hynix Inc.
InventorShin Ho CHU
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device may be effectively evaluated by a test that compares the phase of an internally generated control signal with the phase of an internally generated clock signal. Specifically, if the phase of the internal data strobe signal IDQS is synchronized with the phase of the internal clock signal ICLK through the test, the data strobe signal DQS may also be synchronized with the external clock signal CLK. Thus, the test may prevent certain critical parameters, for example, AC parameter tDQSCK, from being out of an allowable range over PVT (process, voltage, and temperature variation). The test helps ensure that the semiconductor memory device will operate properly in read mode.
Claims24
A semiconductor memory device comprising:
- a delay controller configured to compare a phase of an internal data strobe signal with a phase of an internal clock signal in response to first to third test mode signals and a read command signal to generate delay control signals;
- and
- a clock delay unit configured to delay the internal clock signal by a first delay time according to the delay control signals, and generate a delayed clock signal for creating a data strobe signal.
A semiconductor system comprising:
- a semiconductor memory device configured to compare a phase of an internal data strobe signal with a phase of an internal clock signal to generate a flag signal outputted to a pad, program fuses in response to count signals and to generate fuse signals using the programmed fuses, and delay the internal clock signal by a first delay time controlled according to delayed control signals generated from the count signals or the fuse signals to generate a delayed clock signal for creating a data strobe signal;
- and
- a test circuit configured to receive the flag signal to generate the count signals.
A test method of controlling a parameter, the test method comprising:
- comparing a phase of an internal data strobe signal with a phase of an internal clock signal in response to first to third test mode signals and a read command signal to generate delay control signals;
- and
- delaying the internal clock signal by a first delay time controlled according to the delay control signals to generate a delayed clock signal for creating a data strobe signal.
Dependencies are inferred from the claim text.