US 2014/0177311 A1 · MEMORY DEVICE STRUCTURE WITH DECODERS IN A DEVICE LEVEL SEPARATE FROM THE ARRAY LEVEL

Abstract

A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells.

Claims20

Dependent claims

A memory device comprising:

an array of memory cells in an array level, the array of memory cells having sides that define a perimeter;
an x-decoder and a y-decoder in a device level, one or both of the x-decoder and the y-decoder being disposed at least partly within a cylinder defined by the perimeter;
and
a plurality of inter-level conductive lines connecting the x-decoder and the y-decoder in the device level to bit lines and word lines in the array level, the inter-level conductive lines having portions that extend from outside of the cylinder to inside of the cylinder to make contact in the array level.

1 more element

Dependencies are inferred from the claim text.

Memory device structure with decoders in a device level separate from the array level

Life of this patent

Memory device structure with decoders in a device level separate from the array level

Life of this patent

Abstract

Claims20