US 2014/0177189 A1Published application

Chip stacking structure

AssigneeIndustrial Technology Research Institute

InventorsChang-Chih Liu, Hsun Yu, Peng-Shu Chen, Shih-Hsien Wu

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Abstract

A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

Claims17

Dependent claims

A chip stacking structure, comprising:

a plurality of microbump structures;
a plurality of first substrates, stacked upon each other by a first part of the microbump structures, and each of the first substrates comprises at least one first redistribution layer;
at least one first space layer, located between the first substrates, wherein the first part of the microbump structures is disposed in the at least one first space layer, and is configured to connect the at least one first redistribution layer of the first substrates;
a plurality of second substrates, stacked on at least one of the first substrates by a second part of the microbump structures, and each of the second substrates comprises at least one second redistribution layer;
and
at least one second space layer, located between the first substrates and the second substrates, wherein the second part of the microbump structures is disposed in the at least one second space layer, and is configured to connect the at least one first redistribution layer of the first substrates and the at least one second redistribution layer of the second substrates,
wherein the first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/912,207Filed 7 Jun 2013
Priority: TW 10114988625 Dec 2012
Published: 26 Jun 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification30 codes

H10W 90/00
Package configurations
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 20/212
Through-semiconductor vias, e.g. TSVs: top-view shapes or dispositions, e.g. top-view layouts of the vias
H10W 20/496
Capacitive arrangements or effects of, or between wiring layers: capacitor integral with wiring layers