US 2014/0176586 A1 · MULTI-MODE MEMORY ACCESS TECHNIQUES FOR PERFORMING GRAPHICS PROCESSING UNIT-BASED MEMORY TRANSFER OPERATIONS

Abstract

This disclosure describes techniques for performing memory transfer operations with a graphics processing unit (GPU) based on a selectable memory transfer mode, and techniques for selecting a memory transfer mode for performing all or part of a memory transfer operation with a GPU. In some examples, the techniques of this disclosure may include selecting a memory transfer mode for performing at least part of a memory transfer operation, and performing, with a GPU, the memory transfer operation based on the selected memory transfer mode. The memory transfer mode may be selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode. The techniques of this disclosure may be used to improve the performance of GPU-assisted memory transfer operations.

Claims50

Dependent claims

A method comprising:

selecting, with one or more processors, a memory transfer mode for performing at least part of a memory transfer operation, the memory transfer mode being selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode;
and
performing, with a graphics processing unit (GPU), the memory transfer operation based on the selected memory transfer mode.

A computer-readable storage medium storing instructions that, when executed, cause one or more processors to:

select a memory transfer mode for performing at least part of a memory transfer operation, the memory transfer mode being selected from a set of at least two different memory transfer modes that includes an interleave memory transfer mode and a sequential memory transfer mode;
and
perform the memory transfer operation based on the selected memory transfer mode.

Dependencies are inferred from the claim text.

Facts

Application

13/725,393Filed 21 Dec 2012

Published

26 Jun 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G09G 5/363
Characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory: graphics controllers
G06F 12/0607
Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication: interleaved addressing
G06F 12/0875
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with…
G09G 5/393
Control of the bit-mapped memory: arrangements for updating the contents of the bit-mapped memory

Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations

Life of this patent

Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations

Life of this patent

Abstract

Claims50