Reference charge cancellation for analog-to-digital converters

An analog-to-digital converter (ADC) comprising:

• a switched capacitor bank for sampling an input signal of the ADC;
• logic configured to estimate a change in voltage to the switched capacitor bank to more closely approximate a digital bit, the logic further configured to send a command to initiate a voltage reference hit to cause the change in voltage and to generate a state clock that transitions with sending the command;
• a bypass capacitor connected with the switched capacitor bank to provide the change in voltage to the switched capacitor bank;
• and
• a cancellation circuit connected with the logic and configured to, at the transition of the state clock, adjust a reference voltage of the bypass capacitor to reverse, at least in part, the change in the voltage of the bypass capacitor due to the reference hit.

An analog-to-digital converter (ADC) comprising:

• a switched capacitor bank for sampling an input signal of the ADC;
• first logic configured to estimate a change in voltage to the switched capacitor bank to more closely approximate a digital bit, the first logic further configured to send a command to initiate a voltage reference hit to cause the change in voltage and to generate a state clock that transitions with sending the command;
• a bypass capacitor connected with the switched capacitor bank to provide the change in voltage to the switched capacitor bank;
• a voltage comparator connected with the first logic and configured to generate an output comprising a resolved bit;
• and
• a cancellation circuit connected with the first logic and comprising multiple switches, connected in parallel, and second logic to close one of the switches responsive to a value of the resolved bit to, at the transition of the state clock, adjust the voltage of the bypass capacitor to at least partially offset the change in voltage of the bypass capacitor due to the reference hit.