Method of dynamic element matching and an apparatus thereof
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Global Unichip Corporation
InventorsWen-Hsien Chuang, Hsiang-Wei Liu, Jen-Wei Tsai, Ting-Hao Wang
Life of this patent
Estimating the term…
Abstract
A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.
Claims14
A method for reducing integral nonlinearity (INL) of a digital-to-analog converter (DAC), wherein the DAC comprises a clock for defining a period of said DAC, an input port for receiving an input signal in each period, and N 1-bit DAC for outputting signal, wherein N is a positive integer, the method comprising the step of:
- A. providing a priority sequence of the N 1-bit DACs, wherein the priority sequence defines the priority of each of the N 1-bit DACs;
- B. determining a set among the N 1-bit DACs for outputting according to the priority sequence and the input signal in each period;
- and
- C. re-assigning the priority sequence after a first number of periods, wherein a second number of current sources with the highest priority is set to be with the lowest priority, and the second number is no less than one.
A digital-to-analog converter (DAC), comprising:
- a clock signal for defining an operating period of the DAC;
- a first number of current sources for outputting current, wherein the current of each of the first number of current source is roughly identical;
- an input port for receiving an N-bit input signal, wherein the N-bit input signal determines a second number of the first number of current source for outputting current, wherein the second number is a positive integer;
- a current selector for generating a priority sequence in a third number of operating period, wherein the priority sequence defines a priority of each of the first number of current source to be selected for outputting current, wherein when the priority sequence is generated, a fourth number of current source with the highest priority is set to be with the lowest priority;
- and
- a decoder for selecting one or more of the first number of current sources for outputting current according to the N-bit input signal and the priority sequence in every operating period.
Dependencies are inferred from the claim text.