US 2014/0176230 A1 · High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices

Abstract

A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.

Claims13

Dependent claims

1-21. (canceled)

A method for generating a reference signal that is substantially constant over a prescribed range of process, supply voltage and temperature conditions, the method comprising steps of:

providing a high-voltage tolerant reference circuit that utilizes low voltage transistors, the reference circuit being adapted to receive first and second bias signals and being operative to generate the reference signal, a magnitude of the reference signal being controlled as a function of the first and second bias signals;
generating the first and second bias signals such that when the magnitude of the reference signal is within prescribed limits of a quiescent value of the reference signal, a magnitude of a current in the reference circuit is substantially constant and below a first value, and when the magnitude of the reference signal is outside of the prescribed limits, the magnitude of the current in the reference circuit increases nonlinearly above the first value to thereby restore the magnitude of the reference signal to within the prescribed limits of its quiescent value.

Dependencies are inferred from the claim text.

Facts

Application

14/192,825Filed 27 Feb 2014

Priority

8 Nov 2012

Published

26 Jun 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification3 codes

G05F 3/16
Using uncontrolled devices with non-linear characteristics: being semiconductor devices
G05F 3/24
Using diode- transistor combinations: wherein the transistors are of the field-effect type only
G05F
Systems for regulating electric or magnetic variables

High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices

Life of this patent

High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices

Life of this patent

Abstract

Claims13