Integrated circuit comprising a clock tree cell

Integrated circuit, comprising:

• a semiconductor substrate lying essentially in a plane called the substrate plane;
• a first semiconductor well lying in a plane called the well plane parallel to the substrate plane;
• a plurality of standard cells placed next to one another, each standard cell comprising a first field-effect transistor in FDSOI technology, the first transistor comprising a first semiconductor ground plane located immediately on the first well so as to make electrical contact with the first well, the first well thus being common to all the standard cells placed next to one another;
• a clock tree cell contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, the second transistor comprising a second semiconductor ground plane located immediately on the first well so as to form a p-n junction with this first well, this second ground plane having, for this purpose, an opposite doping type to the doping of the first well;
• and
• an electrical power supply network able to apply separate electrical biases directly to the first and second ground planes.