Sense amplifier including a level shifter

A non-transitory computer-readable medium including program code that, when executed by a processor, causes the processor to retrieve data from a memory, wherein the memory includes:

• a sense amplifier to generate a sense amplifier differential output signal, wherein the sense amplifier is in a first power domain;
• a level shifter to generate a level shifter differential output signal responsive to the sense amplifier differential output signal, wherein the level shifter includes a first pair of transistors including a first transistor and a second transistor, wherein a first sense amplifier output signal of the sense amplifier differential output signal is provided to the first transistor, and wherein a second sense amplifier output signal of the differential output signal is provided to the second transistor, and
• a latch to store data responsive to the level shifter differential output signal, wherein the latch is in a second power domain that is different from the first power domain.

An apparatus comprising:

• a sense amplifier having a sense amplifier differential output, wherein the sense amplifier is in a first power domain;
• level shifting circuitry having a level shifter differential output and coupled to the sense amplifier differential output, wherein the level shifting circuitry includes a first pair of transistors including a first transistor and a second transistor, wherein a first sense amplifier output of the sense amplifier differential output is coupled to the first transistor, and wherein a second sense amplifier output of the sense amplifier differential output is coupled to the second transistor, and
• a driver coupled to the level shifter differential output, wherein the driver is in a second power domain that is different from the first power domain.