Method of implementing clock skew and integrated circuit adopting the same

An integrated circuit comprising:

• a clock distribution network including a clock mesh configured to provide one or distributed clock signals;
• one or more slow clock gates configured to receive the distributed clock signals and to output clock signals having delays aligned to a base latency;
• one or more fast clock gates configured to receive the distributed clock signals and to output clock signals having delays aligned to a minimum pull latency smaller than the base latency;
• one or more buffer networks configured to delay the clock signals from the slow clock gates and the fast clock gates and to provide local clock signals having target latencies, respectively;
• and
• end-point circuits configured to receive the local clock signals, respectively, from the slow clock gates, the fast clock gates or the buffer networks.

A method of implementing a clock skew in an integrated circuit, the method comprising:

• providing a basic placement design for the integrated circuit, wherein the basic placement design includes a list of end-point circuits, a library of clock gates, and a library of buffers;
• establishing a clock distribution network based on the basic placement design to provide an initial placement design, wherein the clock distribution network is connected to the end-point circuits via the clock gates;
• performing skew scheduling on the basic placement design to provide target latencies of local clock signals from the clock gates;
• and
• implementing the clock skew by disposing at least one of the buffers between the clock gates and the end-point circuits based on the initial placement design and the target latencies.