Programmable delay generator and cascaded interpolator
AssigneeInternational Business Machines Corporation
InventorSergey V. Rylov
Life of this patent
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Abstract
A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.
Claims9
A cascaded interpolator, comprising:
- a plurality of single-bit interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate therefrom two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals, each of said single-bit interpolator stages comprising a 2:1 multiplexer and a 1:1 interpolator;
- and
- a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.
A method for cascaded interpolation, comprising:
- forming a plurality of single-bit interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate therefrom two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals, wherein forming each of said single-bit interpolator stages comprises forming a 2:1 multiplexer and a 1:1 interpolator;
- and
- forming a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.
Dependencies are inferred from the claim text.