Clock generation circuit and clock generation system using the same

A clock generation circuit comprising:

• a counting code generation unit configured to generate first codes and second codes in response to an oscillator signal and an input clock when an enable signal is enabled, and output the second codes as counting codes;
• a control code generation unit configured to decode the counting codes and generate control codes;
• and
• a cycle changeable oscillation unit configured to determine a delay time in response to the control codes, and generate an output clock which has a cycle corresponding to the determined delay time.

A clock generation system comprising:

• a counting code generation unit configured to generate a counting code in relation to a frequency of an input clock;
• a control code generation unit configured to generate bit signals;
• and
• a cycle changeable oscillation unit configured to output a frequency from an output clock.