Delay locked loop and semiconductor apparatus
AssigneeSK hynix Inc.
InventorKwan Dong KIM
Life of this patent
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Abstract
A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code.
Claims20
A delay locked loop comprising:
- a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal;
- a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal;
- a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code;
- and
- is a delay code generation unit configured to control the delay code in response to the calculation code.
A semiconductor apparatus comprising:
- a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal;
- a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay is locked loop clock signal as a feedback clock signal;
- a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code;
- a division unit configured to divide the reference clock signal by a predetermined multiple and generate a divided clock signal;
- and
- a delay code generation unit configured to receive the calculation code and update the delay code, in synchronization with the divided clock signal.
Dependencies are inferred from the claim text.