Time-interleaved digital-to-time converter

A method comprising:

• dividing an input clock signal in a divider circuit by integer values to generate a divided clock signal;
• charging a first capacitor with a first current based on a first quantization error associated with a first integer divide value for the divider circuit;
• charging the first capacitor with a second current having a fixed value;
• generating a first pulse of an output clock in response to the first capacitor charging to a predetermined level;
• charging a second capacitor with a third current based on a second quantization error associated with a second integer divide value for the divider circuit;
• charging the second capacitor with a fourth current having the fixed value;
• and
• generating a second pulse of the output clock signal based on the second capacitor charging to the predetermined level.

A method comprising;

• supplying a clock signal to a fractional-N divider circuit and supplying a divided clock signal from the fractional-N divider circuit;
• charging a first capacitor with a first current corresponding to a first digital quantization error during a first portion of a first period of the divided clock signal and charging a second capacitor during a first portion of a next period of the divided clock signal with a second current corresponding to a second digital quantization error;
• charging the first capacitor with the third current having a fixed value during the first period of the divided clock signal and charging the second capacitor with a fourth current having the fixed value during the next period of the divided clock signal;
• generating a first edge of a first pulse of the adjusted divided clock signal in response to the first capacitor charging to a predetermined voltage;
• generating a first edge of a next pulse of the adjusted divided clock signal in response to the second capacitor charging to the predetermined voltage;
• and
• supplying an adjusted divided clock signal including the first and the next pulse respectively having delays linearly proportional to the first and second digital quantization errors.