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US 2014/0176193 A1Published application
Low power squelch detector circuit
AssigneeIntel Corporation
InventorsMichael V. De Vita, Roan M. Nicholson, Shenggao Li
Life of this patent
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Abstract
Described is an apparatus comprising: a reference generator to provide a first reference and a second reference; a first input coupled to the first reference; a second input coupled to the second reference; and a comparator coupled to the first and second inputs, the comparator to receive a clock signal and to update an output signal according to a phase of the clock signal.
Claims20
An apparatus comprising:
- a reference generator to provide a first reference and a second reference;
- a first input coupled to the first reference;
- a second input coupled to the second reference, wherein the first reference is different from the second reference;
- and
- a comparator coupled to the first and second inputs, the comparator to receive a clock signal and to update an output signal according to a phase of the clock signal.
2 more elements
An apparatus comprising:
- a ring oscillator to generate a clock signal;
- and
- a sense amplifier latch to receive differential input signals and to determine a difference between the differential input signals with respect to a difference between first and second references in response to a phase of the clock signal, wherein the first reference is different from the second reference.
A system comprising:
- a memory;
- and
- a processor, coupled to the memory, having an input-output (I/O) receiver for coupling with another processor, the I/O receiver including a squelch detector to detect a signal on an I/O pad coupled to the I/O receiver, wherein the squelch detector comprises:
- a reference generator to provide a first reference and a second reference;
- a first input coupled to the first reference;
- a second input coupled to the second reference, wherein the first reference is different from the second reference;
- and
- a comparator coupled to the first and second inputs, the comparator to receive a clock signal and to update an output signal according to a phase of the clock signal.
5 more elements
Dependencies are inferred from the claim text.