Coarse gating of clock tree elements
AssigneeAdvanced Micro Devices, Inc.
InventorsEric Quinnell, Christopher Thomas
Life of this patent
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Abstract
Methods relating to distribution of a clock signal to logic devices of an integrated circuit. The method includes controlling, by a logic element, the distribution of a clock signal by a dock gater and distributing the clock signal by the clock gater to at least one first logic device, wherein the logic element allows the first clock gater to distribute the clock signal only when at least one first logic device requires the clock signal. An integrated circuit configured to perform such a method. Fabrication of such an integrated circuit.
Claims20
An integrated circuit device, comprising:
- a clock spine to distribute a clock signal;
- a first clock gater to receive the clock signal from the clock spine and distribute the clock signal;
- a logic element to control the distribution of the clock signal by the first clock gater;
- a plurality of second clock gaters, each to receive the clock signal from the first clock gater and distribute the clock signal;
- and
- a plurality of first logic elements, wherein each said first logic element receives the clock signal from one of the plurality of second clock gaters;
- wherein the logic element allows the first clock gater to distribute the clock signal only when at least one said first logic device requires the clock signal.
A method, comprising:
- distributing a clock signal by a clock spine;
- receiving the clock signal by a first clock gater;
- distributing the clock signal by the first clock gater;
- receiving the clock signal by a plurality of second clock gaters;
- distributing the clock signal by a said second clock gater;
- and
- receiving the clock signal by a plurality of first logic devices, wherein each said first logic device is configured to receive the clock signal from the second clock gater;
- wherein the distributing by the first clock gater is performed only if at least one first logic device requires the clock signal, and wherein the distributing is performed by one said second clock gater only if at least one first logic device requires the clock signal.
A computer readable storage device encoded with data that, when executed by a computer system in a manufacturing facility, adapts the manufacturing facility to create an apparatus, comprising:
- a clock spine to distribute a clock signal;
- a first clock gater to receive the clock signal from the clock spine and distributing the clock signal;
- a logic element to control the distribution of the clock signal by the first clock gater;
- a plurality of second clock gaters, each to receive the clock signal from the first clock gater and to distribute the clock signal;
- and
- a plurality of first logic devices, wherein each said first logic device receives the clock signal from one of the plurality of second clock gaters;
- wherein the logic element is configured to allow the first clock gater to distribute the clock signal only when at least one said first logic device requires the clock signal.
Dependencies are inferred from the claim text.