Heterogeneous high-speed serial interface system architecture
AssigneeAltera Corporation
InventorsSurinder SINGH, Wai-Bor LEUNG, Henry Y. LUI, Arch ZALIZNYAK
Life of this patent
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Abstract
One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.
Claims20
An integrated circuit comprising:
- a plurality of four-channel serial interface modules, wherein each of the plurality of four-channel serial interface modules includes
- a first physical medium attachment (PMA) channel circuit,
- a second PMA channel circuit adjacent to the first PMA channel circuit,
- a third PMA channel circuit adjacent to the second PMA channel circuit,
- a fourth PMA channel circuit adjacent to the third PMA channel circuit, and
- at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits.
A four-channel serial interface circuit module comprising:
- a first physical medium attachment (PMA) channel circuit;
- a second PMA channel circuit adjacent to the first PMA channel circuit;
- a third PMA channel circuit adjacent to the second PMA channel circuit;
- a fourth PMA channel circuit adjacent to the third PMA channel circuit;
- a first physical coding sub-layer (PCS) channel circuit programmably coupled to communicate with the first PMA channel circuit;
- a second PCS channel circuit adjacent to the first PCS channel circuit in the physical layout of the integrated circuit and programmably coupled to communicate with the second PMA channel circuit;
- a third PCS channel circuit adjacent to the second PCS channel circuit in the physical layout of the integrated circuit and programmably coupled to communicate with the third PMA channel circuit;
- and
- a fourth PCS channel circuit adjacent to the third PCS channel circuit in the physical layout of the integrated circuit and programmably coupled to communicate with the fourth PMA channel circuit,
- wherein at least two of the first, second, third and fourth PMA channel circuits is programmable to one configuration of a set of configurations consisting of a data-channel configuration and a clock-multiplier-unit configuration.
A method of configuring an integrated circuit, the method comprising configuring a plurality of four-channel serial interface modules to implement a plurality of different serial interface protocols, wherein each of the plurality of four-channel serial interface modules has four physical medium attachment (PMA) channel circuits, four physical coding sub-layer (PCS) circuits programmably coupled to the four PMA channel circuits, and at least one phase-locked loop (PLL) circuit which is programmably coupled to the four PMA channel circuits.
Dependencies are inferred from the claim text.