Back to results
US 2014/0176183 A1Published application
Minimum-spacing circuit design and layout for pica
AssigneeInternational Business Machines Corporation
InventorsHerschel A. Ainspan, SEONGWON KIM, FRANCO STELLARI, ALAN J. WEGER
Life of this patent
Estimating the term…
Abstract
PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.
Claims29
A circuit, comprising:
- a first semiconductor device and a second semiconductor device which emit light during operation, laid out such that light-emitting regions of the respective semiconductor devices are proximal to one another with a gap between the respective light-emitting regions including a target resolution size.
A circuit, comprising:
- a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.
A test circuit, comprising:
- a plurality of test cells arranged in a line, each test cell comprising a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.
A circuit, comprising:
- a first semiconductor device and a second semiconductor device which emit light during operation, laid out such that light-emitting regions of the respective semiconductor devices are proximal to one another with a gap between the respective light-emitting regions including a target resolution size;
- and
- a logic circuit configured to accept an input signal and at least one select signal and to bias light-emitting regions of at least one of the respective semiconductor to inhibit an optical emission when said at least one semiconductor device is triggered.
A circuit, comprising:
- a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
- a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal;
- and
- a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
- wherein one of said NOR gates biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.
2 more elements
A test circuit, comprising:
- a plurality of test cells arranged in a line, each test cell comprising:
- a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology;
- a first NOR gate having an output connected to the drain region of the first transistor and accepting a first select signal and an input signal provided by the output of a previous test cell;
- and
- a second NOR gate having an output connected to the drain region of the second transistor and accepting a second select signal and the input signal,
- wherein one of said NOR gates in each test cell biases the connected transistor's drain region, according to the select signal of said NOR gate, to inhibit an optical emission when said connected transistor is triggered.
3 more elements
Dependencies are inferred from the claim text.