Semiconductor apparatus
AssigneeSK hynix Inc.
InventorsYoung Suk SEO, Ho Uk SONG, Jun Hyun CHUN, Tae Jin KANG
Life of this patent
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Abstract
A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
Claims19
A semiconductor apparatus comprising:
- an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode;
- a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode;
- and
- a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
A semiconductor apparatus comprising:
- an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode;
- a test output timing controller configured to determine a delay amount by inputting a reference clock signal obtained by dividing an external clock signal by a value N into a DLL, delay the applied external read command by the delay amount when the DLL is locked, shift the delayed applied external read command by a CL code in synchronization with a DLL clock signal, and output the shifted delayed applied external read command as a test output enable flag signal, during a test mode;
- and
- a MUX configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.
Dependencies are inferred from the claim text.