Electrical characteristics of package substrates and semiconductor packages including the same
AssigneeSK hynix Inc.
InventorsEul Chul JANG, Qwan Ho CHUNG, Sang Joon LIM, Sung Woo HAN
Life of this patent
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Abstract
Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.
Claims27
A package substrate comprising:
- a power line and a ground line configured on a first surface of a substrate body;
- a couple of signal lines on the first surface between the power line and the ground line;
- and
- a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface,
- wherein the lower ground pattern is disposed to be opposite to the power line and the lower power pattern is disposed to be opposite to the ground line.
A semiconductor package comprising:
- a semiconductor chip mounted on a package substrate,
- wherein the package substrate comprises:
- a power line and a ground line disposed on a first surface of a substrate body and electrically connected to the semiconductor chip;
- and
- a lower ground pattern and a lower power pattern configured on a second surface of the substrate body opposite to the first surface,
- wherein the lower ground pattern is disposed to be opposite to the power line and the lower power pattern is disposed to be opposite to the ground line.
A semiconductor package comprising:
- a power line and a ground line disposed on a first surface of the semiconductor package to prevent noise from occurring between a plurality of signal lines disposed on the first surface;
- and
- a lower ground pattern and a lower power pattern disposed on a second surface of the semiconductor package, wherein the lower ground pattern is disposed under the power line and the lower power pattern is disposed under the ground line.
Dependencies are inferred from the claim text.