Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsKILSOO KIM, SunWon KANG
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AssigneeSamsung Electronics Co., Ltd.
InventorsKILSOO KIM, SunWon KANG
Estimating the term…
A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.
A semiconductor package, comprising:
14-35. (canceled)
Dependencies are inferred from the claim text.
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Package configurations
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers
Characterised by their interconnections: vias, e.g. via plugs
Characterised by their interconnections: shapes or dispositions of interconnections
Term end not estimated
This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0149602, filed on Dec. 20, 2012, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
Example embodiments of the inventive concepts relate to a semiconductor device, and in particular, to a semiconductor package.
There is a growing trend to fabricate lightweight, small-sized, high speed, multifunctional, high performance, and low-cost electronic systems. In response to such a trend, multi-chip stacked package techniques and/or system in package techniques have been proposed. In a multi-chip stacked package or a system in package, one or more functions of a plurality of semiconductor devices may be performed in a single semiconductor package. The multi-chip stacked package or the system in package may have a thickness larger than that of a single chip package, but may have a similar size to the single chip package in terms of a planar surface area or “footprint”. Thus, the multi-chip stacked package or the system in package may be used in smaller (e.g., mobile) devices with high performance requirements such as, for example, mobile phones, notebook computers, memory cards, portable camcorders, and the like.
Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.
FIG. 1 is a schematic diagram illustrating a semiconductor package according to example embodiments of the inventive concepts.
FIG. 2A is a sectional view of a semiconductor package according to a first embodiment of the inventive concepts.
It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.
Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus redundant descriptions may be omitted.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements or layers should be interpreted using the same principles discussed above (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”). As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.