Anchoring a trace on a substrate to reduce peeling of the trace

Abstract

Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer.

Dependencies are inferred from the claim text.