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US 2014/0175652 A1Published application
Barrier for Through-Silicon Via
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
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Abstract
A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).
Claims20
A semiconductor device comprising:
- a semiconductor substrate having a first major surface and a second major surface;
- at least one metallization layer formed on the first major surface;
- a transistor formed at least partially in the substrate proximate the first major surface;
- a through substrate via (TSV) extending from the first major surface to the second major surface and being in electrical communication with the at least one metallization layer, the TSV including:
- sidewalls extending from the first major surface to the second major surface,
- a barrier layer disposed along the sidewalls, the barrier layer including a metal component and an alloying material, wherein the alloying material comprises carbon and is less than approximately 15% of the barrier layer, and
- a conductive material extending from the first major surface to the second major surface, the conductive material being in electrical communication with the at least one metallization layer;
- and
- a contact electrically coupling the transistor and the at least one metallization layer.
6 more elements
A method comprising:
- forming on a first surface of a semiconductor substrate an integrated circuit device;
- forming over the first surface a dielectric layer;
- etching an opening through the dielectric layer and at least partially through the substrate, the opening have sidewalls;
- conformally forming a barrier layer on the sidewalls, wherein the barrier layer includes a composition having a metal component and a carbon alloying material at a concentration of no greater than about 15% of the barrier layer;
- and
- forming a conductor on the barrier layer, the conductor having a top surface coplanar with a top surface of the dielectric layer and a bottom surface at a bottom surface of the opening proximate a second surface of the substrate.
3 more elements
A method comprising:
- forming at least one active device on a first surface of a semiconductor substrate;
- forming an interlevel dielectric layer (ILD) over the first surface and the at least one active device;
- forming a contact structure extending through the ILD and electrically contacting the at least one active device;
- etching an opening extending through the ILD and at least partially through the semiconductor substrate, the opening having sidewalls and a bottom
- forming a liner on ILD and on the sidewalls and bottom of the opening;
- forming a barrier layer on the liner by depositing barrier material using a precursor composition having a metal component and a carbon alloying material, the carbon alloying material having a concentration of no greater than about 15% of the barrier material;
- forming an adhesion layer on the barrier layer;
- forming a seed layer on the adhesion layer and electroplating a conductor on the seed layer and filling the opening;
- removing portions of a second surface of the semiconductor substrate to expose the conductor;
- and
- forming an electrical contact on at least one end of the conductor.
8 more elements
Dependencies are inferred from the claim text.