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US 2014/0175643 A1Published application
Apparatuses and methods to enhance passivation and ild reliability
AssigneeIntel Corporation
InventorsRichard J. Harries, Sudarashan V. Rangaraj, Robert L. Sankman
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Abstract
Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.
Claims1
An apparatus comprising:
- a first bump and a second bump on a surface of a substrate;
- a first sidewall structure adjacent to the first bump and on the surface;
- a second sidewall structure adjacent to the second bump and on the surface;
- a gap between the first sidewall structure and the second sidewall structure that exposes at least a portion of the substrate surface;
- and
- a substantially uniform, non-conducting underfill surrounding the first and second sidewall structures.
3 more elements
Dependencies are inferred from the claim text.