Packaging structure
AssigneeInternational Business Machines Corporation
InventorsEvan G. Colgan, Paul W. Coteus, Robert L. Wisnieff
Life of this patent
Estimating the term…
Abstract
A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.
Claims25
A packaging structure, comprising:
- first and second chips;
- at least one surface of each of the first and second chips being an active surface;
- and
- a common chip to which a sidewall of at least one of the first and second chips is electrically interconnected, the sidewall being adjacent and transverse to the active surface;
- the respective active surfaces of the first and second chips being directly electrically interconnected to one another in a face-to-face arrangement and being oriented transversely with respect to the common chip.
A packaging structure, comprising:
- first and second chips, each of the first and second chips including a body having two opposing surfaces and four sidewalls extending between and transversely oriented with respect to the two opposing surfaces;
- at least one of the two opposing surfaces of each of the first and second chips being an active surface;
- and
- a common chip to which at least one of the respective sidewalls of the first and second chips is electrically interconnected;
- the respective active surfaces of the first and second chips being directly electrically interconnected to one another in a face-to-face arrangement and being oriented transversely with respect to the common chip.
A packaging structure, comprising:
- chip sets of at least first and second chips;
- at least one surface of each of the first and second chips of each chip set being an active surface;
- the respective active surfaces of the first and second chips of each of the chip sets being directly electrically interconnected to one another in a face-to-face arrangement;
- a pass-through block disposed in contact with the at least one active surface of the first chip of each chip set and the at least one active surface of the first chip of another chip set and by which the at least one active surface of the first chip of each chip set is electrically interconnected with the at least one active surface of the first chip of another chip set;
- and
- a pass-through block disposed in contact with the at least one active surface of the second chip of each chip set and the at least one active surface of the second chip of another chip set and by which the at least one active surface of the second chip of each chip set is electrically interconnected with the at least one active surface of the second chip of another chip set.
A packaging structure, comprising:
- first and second chip sets, each chip set including at least first and second chips;
- at least one surface of each of the first and second chips of each chip set being an active surface;
- the respective active surfaces of the first and second chips of each of the chip sets being directly electrically interconnected to one another in a face-to-face arrangement;
- a bonding layer by which the first and second chip sets are attached to one another;
- and
- pass-through blocks by which the at least one active surface of the first chip of each chip set is electrically interconnected with the at least one active surface of the first chip of another chip set and the at least one active surface of the second chip of each chip set is electrically interconnected with the at least one active surface of the second chip of another chip set.
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Dependencies are inferred from the claim text.