Stripline and reference plane implementation for interposers using an implant layer

Abstract

An integrated circuit system includes an interposer substrate with an electrical reference plane, or “ground plane,” formed by a conductive semiconductor layer. The conductive semiconductor layer may be formed in a surface region of the interposer substrate, and in some embodiments is formed by performing an ion implant process on the surface region to increase the electrical conductivity of the surface region. Because the surface region is electrically coupled to an electrical ground of the integrated circuit system, the surface region functions as a ground plane that helps contain electric fields produced by signals routed through interconnects of the interposer substrate. Consequently, a ground plane can be formed on a surface of the interposer substrate without forming a metalization layer.

Dependencies are inferred from the claim text.