Varactor
AssigneeIndustrial Technology Research Institute
InventorsSih-Han Li, Pei-Ling Tseng, Zhe-Hui Lin, Chih-Sheng Lin
Life of this patent
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Abstract
A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.
Claims37
A varactor, comprising:
- a substrate, comprising a first surface, a second surface substantially parallel to the first surface, and a first opening and a second opening in the substrate;
- a conductive material, filling the first opening and the second opening to form a first through-wafer via and a second through-wafer via, respectively;
- a first capacitor coupled between the first through-wafer via and a first terminal;
- and
- a second capacitor coupled between the second through-wafer via and a second terminal,
- wherein a capacitance of a first depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.
A varactor, comprising:
- a first wafer, comprising:
- a first substrate, comprising a first surface, a second surface substantially parallel to the first surface, and a first opening and a second opening in the first substrate;
- a first conductive material, filling the first opening and the second opening to form a first through-wafer via and a second through-wafer via, respectively;
- a first conductive layer disposed on the second surface of the first substrate, comprising a first trace coupled to the second through-wafer via;
- and
- a first capacitor coupled between the first through-wafer via and a first terminal;
- and
- a second wafer disposed below the first wafer, comprising:
- a second substrate, comprising a third surface and a fourth surface substantially parallel to the first surface;
- and
- a second conductive layer disposed on the third surface of the second substrate, comprising a second trace coupled to a second terminal,
- wherein a second capacitor is formed by the first trace of the first conductive layer and the second trace of the second conductive layer,
- wherein a capacitance of a first depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via.
Dependencies are inferred from the claim text.