Semiconductor substrate for photonic and electronic structures and method of manufacture

A method of forming an integrated structure, the method comprising:

• using a single reticle in a photolithographic process to pattern an etch mask provided over a semiconductor substrate, the pattern defining openings for etching first trench isolation areas and at least one second trench isolation area in the substrate, the opening for etching the at least one second trench isolation area being wider than the openings for etching the first trench isolation areas;
• removing semiconductor material from the substrate using the first and second openings in the etch mask to provide the first and second trench isolation areas;
• further etching the at least one second trench isolation area to be deeper than the first trench isolation areas;
• filling the first and second trench isolation areas with a dielectric material;
• planarizing the first and second trench isolation areas to the level of the substrate;
• and,
• forming a photonic device on the at least one planarized second trench isolation area.

A method of forming an integrated structure, the method comprising:

• forming first and second dielectric filled trench isolation areas in a semiconductor substrate, which have upper surfaces which are planar with the upper surface of the substrate, the second isolation area being wider and deeper than the first isolation area, the locations of the first and second dielectric filled trench isolation areas being defined by a hard mask patterned by a single reticle;
• forming an electronic device on the substrate which is electrically isolated by the first trench isolation area;
• and
• forming a photonic device on the second trench isolation area, the photonic device being optically isolated from the substrate by the second trench isolation area.

An integrated circuit structure comprising:

• a semiconductor substrate having a planar upper surface;
• a first trench isolation area having a first depth into the substrate from the planar upper surface;
• an electronic device electrically isolated by the first trench isolation area;
• a second trench isolation area having a second depth into the substrate from the planar upper surface, where the second depth is greater than the first depth, the second trench isolation area having a planar upper surface;
• and
• a photonic device on the planar upper surface of the second trench isolation area, the photonic device being optically isolated from the substrate by the second trench isolation area.