Integrated Circuit Cell Library for Multiple Patterning
AssigneeTela Innovations, Inc.
InventorsMichael C. Smayling, Scott T. Becker
Life of this patent
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Abstract
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.
Claims21
A semiconductor chip, comprising:
- a gate electrode level including a first plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the first plurality of linear-shaped conductive structures positioned in accordance with a first pitch such that a distance as measured in a second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the first plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the first pitch,
- the gate electrode level including a second plurality of linear-shaped conductive structures defined to extend lengthwise in the first direction, the second plurality of linear-shaped conductive structures positioned in accordance with a second pitch such that a distance as measured in the second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the second plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the second pitch,
- the second pitch not equal to the first pitch.
A semiconductor chip, comprising:
- a gate electrode level including a first plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the first plurality of linear-shaped conductive structures positioned in accordance with a first pitch such that a distance as measured in a second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the first plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the first pitch,
- the gate electrode level including a second plurality of linear-shaped conductive structures defined to extend lengthwise in the first direction, the second plurality of linear-shaped conductive structures positioned in accordance with a second pitch such that a distance as measured in the second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the second plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the second pitch,
- wherein a position of at least one of the second plurality of linear-shaped conductive structures is offset in the second direction from at least one adjacent of the first plurality of linear-shaped conductive structures.
Dependencies are inferred from the claim text.