Semiconductor device
AssigneeRenesas Electronics Corporation
InventorKen SATOU
Life of this patent
Estimating the term…
Abstract
An increase in chip area and a deterioration of delay performance are reduced without dummy cells or dummy gates for plasma damage, suppressing an increase in the capacitance of dummy cells or dummy gates and a deterioration of wiring. In the case where bit wires or bit contacts used for the DRAM cell region of a circuit block are used as wires and contacts for a logic circuit region, gate electrodes affected by plasma damage are automatically analyzed after the completion of placement and routing. The well contact region (well potential diffusion layer) of the logic circuit region contains dummy contacts for plasma damage.
Claims8
A semiconductor device comprising:
- a well potential diffusion layer disposed in a circuit block having a pattern of a DRAM bit line wiring layer coupled to a gate electrode of a MOSFET via a bit contact;
- and
- dummy bit contacts disposed over the well potential diffusion layer.
A semiconductor device comprising:
- a memory circuit region including:
- a diffusion layer;
- a bit line wiring layer;
- a bit contact formed between said bit line wiring layer and said diffusion layer;
- and
- a logic circuit region including:
- a well potential diffusion layer;
- a first wiring layer coupled to a first transistor;
- a first contact disposed over said well potential diffusion layer,
- wherein said bit line wiring layer and said first wiring layer are formed on the same wiring layer level, the first contact is electrically uncoupled to an upper wiring layer.
Dependencies are inferred from the claim text.