US 2014/0175554 A1Published application

Fully substrate-isolated finfet transistor

AssigneeSTMicroelectronics S.r.l.

InventorsNicolas Loubet, Prasanna Khare

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Abstract

Channel-to-substrate leakage in a FinFET device can be prevented by inserting an insulating layer between the semiconducting channel (fin) and the substrate. Similarly, source/drain-to-substrate leakage in a FinFET device can be prevented by isolating the source/drain regions from the substrate by inserting an insulating layer between the source/drain regions and the substrate. The insulating layer isolates the conduction path from the substrate both physically and electrically, thus preventing current leakage. If an array of semiconducting fins is made up of a multi-layer stack, the bottom material can be removed thus yielding a fin array that is suspended above the silicon surface. A resulting gap underneath the remaining top fin material can then be filled in with oxide to better support the fins and to isolate the array of fins from the substrate. The resulting FinFET device is fully substrate-isolated in both the gate region and the source/drain regions.

Claims18

Dependent claims

A method of forming a FinFET transistor on a silicon substrate, the method comprising:

doping the silicon substrate;
forming an array of raised multi-layer fins extending vertically from the silicon substrate, the raised multi-layer fins including at least a bottom semiconducting material and a top semiconducting material;
depositing a first insulator between the fins to provide local inter-fin isolation;
forming insulating trenches to electrically isolate the FinFET transistor from neighboring regions;
forming a sacrificial gate overlying, and aligned substantially orthogonally to, the array of raised multi-layer fins, the sacrificial gate being contiguous to three sides of each multi-layer fin, a portion of each multi-layer fin located underneath the sacrificial gate operating as a conductive fin channel;
on opposite sides of the sacrificial gate, forming an in-situ doped epitaxial layer in contact with the top semiconducting material;
removing the bottom semiconducting material from the conductive fin channels to create a void between the top semiconducting material and the silicon substrate, the void providing a physical separation between the conductive fin channels and the silicon substrate;
filling the void with a second insulator to electrically insulate the conductive fin channels from the silicon substrate;
and
replacing the sacrificial gate with an operable gate.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/725,528Filed 21 Dec 2012
Published: 26 Jun 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification25 codes

H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 62/822
Heterojunctions: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions