Semiconductor device
AssigneeSeiko Instruments Inc.
InventorsHitomi SAKURAI, Yoshitsugu HIROSE
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Abstract
Provided is a semiconductor device capable of suppressing latch-up generation and formed within a small area. In a minority carrier capture region, a P-type diffusion region (22), an N-type well (24), and a P-type diffusion region (25) are formed on a surface of a P-type semiconductor substrate (27). An N-type diffusion region (23) is formed on a surface of the N-type well (24). And the N-type well (24) is located between the P-type diffusion region (22) and the P-type diffusion region (25). The P-type diffusion region (22) and the P-type diffusion region (25) are each connected to a ground pad (12) not by the shortest distance but respectively through metal film wirings arranged in a diverted way.
Claims4
A semiconductor device, comprising:
- a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad;
- a first N-type diffusion region that is formed on the P-type semiconductor substrate and is connected to the pad;
- a region of an internal circuit that is formed on the P-type semiconductor substrate;
- and
- a minority carrier capture region formed between the first N-type diffusion region and the region of the internal circuit, for capturing minority carriers in the P-type semiconductor substrate caused by a surge to the pad,
- the minority carrier capture region including a triple guard ring including:
- a first P-type diffusion region;
- a second P-type diffusion region;
- and
- a second N-type diffusion region that is located between the first P-type diffusion region and the second P-type diffusion region,
- the first P-type diffusion region and the second P-type diffusion region each being connected to the ground pad respectively through metal film wirings that are separately formed,
- the second N-type diffusion region being connected to the power supply pad.
Dependencies are inferred from the claim text.