High Temperature Gate Replacement Process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Shi Liu, Chen-Hua Yu
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Abstract
A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate.
Claims20
A method comprising:
- forming a gate structure that includes a dummy gate over a substrate;
- removing the dummy gate from the gate structure thereby forming a trench;
- forming a gate electrode in the trench;
- performing a first annealing process to adjust a threshold voltage of the gate electrode;
- after performing the first annealing process, forming a interlayer dielectric layer over the gate electrode;
- removing portions of the interlayer dielectric layer to form a contact opening that extends through the interlayer dielectric layer to expose a portion of the substrate;
- and
- forming a silicide feature on the exposed portion of the substrate, wherein forming the silicide feature includes depositing a metal layer on the exposed portion of the substrate and performing a second annealing process to form the silicide feature.
A method comprising:
- forming a gate structure over a substrate, wherein the gate structure includes a first gate electrode disposed over a first dielectric layer;
- forming a first interlayer dielectric layer over the gate structure;
- removing the first gate electrode from the gate structure thereby forming a trench;
- forming a second gate electrode in the trench;
- performing a first annealing process to adjust a threshold voltage of the second gate electrode;
- removing portions of the first interlayer dielectric layer to form a contact opening that extends through the first interlayer dielectric layer to expose a portion of the substrate;
- and
- forming a silicide feature on the exposed portion of the substrate, wherein forming the silicide feature includes depositing a metal layer on the exposed portion of the substrate and performing a second annealing process to form the silicide feature.
A device comprising:
- a gate structure disposed over a semiconductor substrate;
- a lightly doped source/drain feature disposed within the semiconductor substrate adjacent the gate structure;
- a heavily doped source/drain feature disposed within the semiconductor substrate adjacent the lightly doped source/drain feature;
- a sidewall spacer disposed on a sidewall of the gate structure;
- and
- a silicide feature disposed on the semiconductor substrate over the heavily doped source/drain feature, wherein the silicide feature extends from an outer edge of the sidewall spacer.
Dependencies are inferred from the claim text.