US 2014/0175539 A1 · CANYON GATE TRANSISTOR AND METHODS FOR ITS FABRICATION

Abstract

Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.

Claims20

Dependent claims

A non-planar field effect transistor (FET), comprising:

a semiconductor substrate of a first conductivity type and having a first surface;
a first doped region of a second, opposite, conductivity type located adjacent the first surface, adapted to act as a source or drain, and extending to a first depth beneath the first surface;
a second doped region of the second conductivity type, adapted to act as a drain or a source, located in the substrate at a second depth beneath the first surface greater than the first depth, and coupled to the first doped region by an interior sidewall of the substrate;
a gate conductor adjacent the interior sidewall of the substrate but separated from the sidewall by a gate insulator, and adapted when appropriately biased to form a conductive channel adjacent the sidewall;
and
a first electrical connection coupled to the second doped region, a second electrical connection coupled to the first doped region and a third electrical connection coupled to the gate conductor, wherein the first, second and third electrical connections extend to the first surface.

3 more elements

A non-planar field effect transistor (FET) comprising:

a substrate having a first surface;
a cavity extending into the substrate a first distance to a recessed surface, wherein the cavity is bounded by a first sidewall portion and a second sidewall portion, with each sidewall portion extending between the recessed surface and the first surface;
first doped regions in the substrate proximate the first surface and laterally adjacent to each sidewall portion;
a second doped region in the substrate proximate the recessed surface of the cavity and extending laterally within each sidewall portion;
a gate insulator on each sidewall portion;
a first gate conductor portion in contact with the gate insulator adjacent the first sidewall portion and overlying the second doped region;
a second gate conductor portion in contact with the gate insulator adjacent the second sidewall portion and overlying the second doped region;
a dielectric material between the first gate conductor portion and the second gate conductor portion;
and
first, second and third electrical connections, respectively, to the first doped region, the second doped region and the first gate conductor.

7 more elements

Dependencies are inferred from the claim text.

Canyon gate transistor and methods for its fabrication

Life of this patent

Canyon gate transistor and methods for its fabrication

Life of this patent

Abstract

Claims20