Memory devices capable of reducing lateral movement of charges
AssigneeSamsung Electronics Co., Ltd.
InventorKwang-soo SEOL
Life of this patent
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Abstract
Memory devices are provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.
Claims20
1-10. (canceled)
A memory device, comprising:
- a tunneling insulating layer on an active region;
- a charge storage layer on the tunneling insulating layer;
- a blocking insulating layer on the charge storage layer;
- and
- a control gate electrode on the blocking insulating layer,
- wherein the control gate electrode has an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode, and
- wherein a surface of the control gate electrode, which faces the blocking insulating layer, has a central portion with a pointed inverted triangular sectional structure.
A memory device, comprising:
- a tunneling insulating layer on an active region;
- a charge storage layer on the tunneling insulating layer;
- a blocking insulating layer on the charge storage layer;
- and
- a control gate electrode on the blocking insulating layer,
- wherein the control gate electrode has an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode, and
- wherein a surface of the control gate electrode, which faces the blocking insulating layer, has a convex surface curved towards the blocking insulating layer.
A memory device, comprising:
- a tunneling insulating layer on an active region;
- a charge storage layer on the tunneling insulating layer;
- a blocking insulating layer on the charge storage layer;
- and
- a control gate electrode on the blocking insulating layer,
- wherein the control gate electrode has an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode, and
- wherein the central portion of the control gate electrode has a plane surface opposite the blocking insulating layer, and the edge portion of the control gate electrode has a concave surface that tapers outwards towards a sidewall of the memory device and away from the blocking insulating layer.
Dependencies are inferred from the claim text.