Semiconductor structure and process thereof
AssigneeUnited Microelectronics Corp.
InventorsChung-Fu Chang, Yu-Hsiang Hung, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
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Abstract
A semiconductor structure includes a gate, a dual spacer and two recesses. The gate is located on a substrate. The dual spacer is located on the substrate beside the gate. The recesses are located in the substrate and the dual spacers, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle located in the dual spacer and close to the substrate. The present invention also provides a semiconductor process formed said semiconductor structure.
Claims20
A semiconductor structure, comprising:
- a gate located on a substrate;
- a dual spacer located on the substrate beside the gate;
- and
- two recesses located in the substrate and the dual spacer, wherein the sidewall of each of the recesses next to the gate has a lower tip and an upper tip, and the lower tip is located in the substrate while the upper tip is an acute angle, located in the dual spacer and directly next to the substrate.
A semiconductor process, comprising:
- forming a gate on a substrate;
- forming a dual spacer on the substrate beside the gate;
- and
- performing a first etching process and a second etching process on the substrate and the dual spacer to form two recesses in the substrate and the dual spacer beside the gate, wherein the first etching process is used for etching the substrate beside the dual spacer to form a lower tip of each of the two recesses and the second etching process is used for etching the dual spacer directly next to the substrate to form the upper tip of each of the two recesses, and the upper tip is an acute angle.
Dependencies are inferred from the claim text.