Method and layer structure for preventing intermixing of semiconductor layers
AssigneeIqe Kc, LLC
InventorsKevin S. Stevens, Eric M. Rehder, Charles R. Lutz
Life of this patent
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Abstract
A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers.
Claims41
A semiconductor device, comprising:
- a) a field-effect transistor that includes a first layer of at least one arsenic-based semiconductor and an etch-stop layer;
- b) a bipolar transistor that includes a second layer of at least one arsenic-based semiconductor, wherein the etch-stop layer is between the first and second layers;
- and
- c) a p-type layer between the etch-stop layer and the second layer, whereby the p-type layer inhibits intermixing of the etch-stop layer with at least one of the arsenic-based semiconductor layers.
A Semiconductor device, comprising:
- a) a field effect transistor that includes a first layer of at least one arsenic-based semiconductor;
- b) a bipolar transistor that includes a second layer of at least one arsenic-based semiconductor;
- c) an etch-stop layer between the first and second layers;
- and
- d) a p-type layer between the etch-stop layer and the second layer, whereby the p-type layer inhibits intermixing of the etch-stop layer with at least one of the arsenic-based semiconductor layers.
A method of fabricating a semiconductor device, comprising the steps of:
- a) depositing an etch-stop layer above an arsenic-based semiconductor layer of a field-effect transistor;
- b) depositing a p-type layer above the etch-stop layer;
- and
- c) depositing an arsenic-based semiconductor layer of a bipolar transistor above the p-type layer, thereby creating an electric field that prevents intermixing of the etch-stop layer with at least one of the arsenic-based semiconductor layers.
A method of fabricating a semiconductor device, comprising the steps of:
- a) depositing a field-effect transistor that includes a first layer of at least one arsenic-based semiconductor and an etch-stop layer;
- b) depositing a bipolar transistor that includes a second layer of at least one arsenic-based semiconductor, wherein the etch-stop layer is between the first and second layers;
- and
- c) depositing a p-type layer between the etch-stop layer and the second layer, whereby the p-type layer inhibits intermixing of the etch-stop layer with at least one of the arsenic-based semiconductor layers.
Dependencies are inferred from the claim text.